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| Back CS1124 Dual Variable-Reluctance Sensor Interface IC The CS1124 is a monolithic integrated circuit designed primarily to condition signals used to monitor rotating parts. The CS1124 is a dual channel device. Each channel interfaces to a Variable Reluctance Sensor, and monitors the signal produced when a metal object is moved past that sensor. An output is generated that is a comparison of the input voltage and the voltage produced at the IN Adj lead. The resulting square-wave is available at the OUT pin. When the DIAG pin is high, the reference voltage at INAdj is increased. This then requires a larger signal at the input to trip the comparator, and provides for a procedure to test for an open sensor. http://onsemi.com 8 1 SO-8 D SUFFIX CASE 751 * * * * * Features Dual Channel Capability Built-In Test Mode On-Chip Input Voltage Clamping Works from 5.0 V Supply Accurate Built-In Hysteresis VCC PIN CONNECTIONS AND MARKING DIAGRAM INAdj IN1 IN2 GND A WL, L YY, Y WW, W OUT1 To P + - 1 1124 ALYW 8 VCC OUT1 OUT2 DIAG VCC VCC VCC INP1 DIAG R1 IN1 C1 Active Clamp INAdj VCC = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device CS1124YD8 CS1124YDR8 Package SO-8 SO-8 Shipping 95 Units/Rail 2500 Tape & Reel RRS VRS COMP1 Variable Reluctance Sensor VCC INP2 VCC OUT2 To P + - R2 IN2 C2 Active Clamp RRS VRS COMP2 Variable Reluctance Sensor GND RAdj Figure 1. Block Diagram (c) Semiconductor Components Industries, LLC, 2001 1 April, 2001 - Rev. 6 Publication Order Number: CS1124/D CS1124 MAXIMUM RATINGS* Rating Storage Temperature Range Ambient Operating Temperature Supply Voltage Range (continuous) Input Voltage Range (at any input, R1 = R2 = 22 k) Maximum Junction Temperature ESD Susceptibility (Human Body Model) Lead Temperature Soldering: 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value -65 to 150 -40 to 125 -0.3 to 7.0 -250 to 250 150 2.0 230 peak Unit C C V V C kV C ELECTRICAL CHARACTERISTICS (4.5 V < VCC < 5.5 V, -40C < TA < 125C, VDIAG = 0; unless otherwise specified.) Characteristic VCC SUPPLY Operating Current Supply Sensor Inputs Input Threshold - Positive Input Threshold - Negative Input Bias Current (INP1, INP2) Input Bias Current (DIAG) Input Bias Current Factor (KI) (INAdj = INP x KI) Bias Current Matching Input Clamp - Negative Input Clamp - Positive Output Low Voltage Output High Voltage Mode Change Time Delay Input to Output Delay Output Rise Time Output Fall Time Open-Sensor Positive Threshold Logic Inputs DIAG Input Low Threshold DIAG Input High Threshold DIAG Input Resistance - - VIN = 0.3 x VCC , VCC = 5.0 V VIN = VCC, VCC = 5.0 V - 0.7 x VCC 8.0 8.0 - - 22 22 0.2 x VCC - 70 70 V V k k IOUT = 1.0 mA CLOAD = 30 pF CLOAD = 30 pF VDIAG = High, RIN(Adj) = 40 k. Note 2 VDIAG = Low VDIAG = High VDIAG = Low VDIAG = High VIN = 0.336 V VDIAG = 0 V VIN = 0.336 V, VDIAG = Low VIN = 0.336 V, VDIAG = High INP1 or INP2 to INAdj, VIN = 0.336 V IIN = -50 A IIN = -12 mA IIN = +12 mA IOUT = 1.6 mA IOUT = -1.6 mA - 135 135 -185 135 -16 - - 152 -1.0 -0.5 -0.5 5.0 - VCC - 0.5 0 - - - 29.4 160 160 -160 160 -11 - 100 155 0 -0.25 -0.30 7.0 0.2 VCC - 0.2 - 1.0 0.5 0.05 54 185 185 -135 185 -6.0 1.0 - 157 1.0 0 0 9.0 0.4 - 20 20 2.0 2.0 86.9 mV mV mV mV A A %INP %INP A V V V V V s s s s k VCC = 5.0 V - - 5.0 mA Test Conditions Min Typ Max Unit 2. This parameter is guaranteed by design, but not parametrically tested in production. http://onsemi.com 2 CS1124 PACKAGE PIN DESCRIPTION* PACKAGE PIN # SO-8 1 2 3 4 5 6 7 8 PIN SYMBOL INAdj IN1 IN2 GND DIAG OUT2 OUT1 VCC FUNCTION External resistor to ground that sets the trip levels of both channels. Functions for both diagnostic and normal mode. Input to channel 1. Input to channel 2. Ground. Diagnostic mode switch. Normal mode is low. Output of channel 2. Output of channel 1. Positive 5.0 volt supply input. VCC VCC INP1 DIAG R1 C1 IN1 VCC VCC VCC OUT1 To P + - INAdj RRS VRS Active Clamp COMP1 Variable Reluctance Sensor GND RAdj Figure 2. Application Diagram THEORY OF OPERATION NORMAL OPERATION Figure 2 shows one channel of the CS1124 along with the necessary external components. Both channels share the INAdj pin as the negative input to a comparator. A brief description of the components is as follows: VRS - Ideal sinusoidal, ground referenced, sensor output - amplitude usually increases with frequency, depending on loading. RRS - Source impedance of sensor. R1/RAdj - External resistors for current limiting and biasing. INP1/INAdj - Internal current sources that determine trip points via R1/RAdj. COMP1 - Internal comparator with built-in hysteresis set at 160 mV. OUT1 - Output 0 V - 5.0 V square wave with the same frequency as VRS. By inspection, the voltage at the (+) and (-) terminals of COMP1 with VRS = 0V are: V+ + INP1(R1 ) RRS) (1) http://onsemi.com 3 CS1124 V- + INAdj RAdj (2) OPEN SENSOR PROTECTION The CS1124 has a DIAG pin that when pulled high (5.0 V), will increase the INAdj current source by roughly 50%. Equation (7) shows that a larger VRS(+TRP) voltage will be needed to trip comparator COMP1. However, if no VRS signal is present, then we can use equations 1, 2, and 4 (equation 5 does not apply in this mode) to get: INP1(R1 ) RRS) u INP1 KI RAdj ) VHYS (12) As VRS begins to rise and fall, it will be superimposed on the DC biased voltage at V+. V+ + INP1(R1 ) RRS) ) VRS (3) To get comparator COMP1 to trip, the following condition is needed when crossing in the positive direction, V+ u V- ) VHYS (4) (VHYS is the built-in hysteresis set to 160 mV), or when crossing in the negative direction, V+ t V- * VHYS (5) Since RRS is the only unknown variable we can solve for RRS, RRS + INP1 KI RAdj ) VHYS * R1 INP1 (13) Combining equations 2, 3, and 4, we get: INP1(R1 ) RRS) ) VRS u INAdj RAdj ) VHYS (6) therefore, VRS(+TRP) t INAdj RAdj * INP1(R1 ) RRS) ) VHYS (7) Equation (13) shows that if the output switches states when entering the diag mode with VRS = 0, the sensor impedance must be greater than the above calculated value. This can be very useful in diagnosing intermittent sensor. INPUT PROTECTION As shown in Figure 2, an active clamp is provided on each input to limit the voltage on the input pin and prevent substrate current injection. The clamp is specified to handle 12 mA. This puts an upper limit on the amplitude of the sensor output. For example, if R1 = 20 k, then VRS(MAX) + 20 k 12 mA + 240 V It should be evident that tripping on the negative side is: VRS(-TRP) t INAdj RAdj * INP1(R1 ) RRS) * VHYS (8) In normal mode, INP1 + INAdj (9) We can now re-write equation (7) as: VRS(+TR) u INP1(RAdj * R1 * RRS) ) VHYS (10) By making RAdj + R1 ) RRS (11) you can detect signals with as little amplitude as VHYS. A design example is given in the applications section. Therefore, the VRS(pk-pk) voltage can be as high as 480 V. The CS1124 will typically run at a frequency up to 1.8 MHz if the input signal does not activate the positive or negative input clamps. Frequency performance will be lower when the positive or negative clamps are active. Typical performance will be up to a frequency of 680 kHz with the clamps active. http://onsemi.com 4 CS1124 CIRCUIT DESCRIPTION Figure 3 shows the part operating near the minimum input thresholds. As the sin wave input threshold is increased, the low side clamps become active (Figure 4). Increasing the amplitude further (Figure 5), the high-side clamp becomes active. These internal clamps allow for voltages up to -250 V and 250 V on the sensor side of the setup (with R1 = R2 = 22 k) (reference the diagram page 1). Figure 6 shows the effect using the diagnostic (DIAG) function has on the circuit. The input threshold (negative) is switched from a threshold of -160 mV to +160 mV when DIAG goes from a low to a high. There is no hysteresis when DIAG is high. OUT1, 2.0 V/div IN1, 5.0 V/div 20 ms/div IN1, 200 mV/div Figure 5. Low- and High-Side Clamps DIAG 5.0 V/div OUT1, 2.0 V/div IN1 1.0 V/div 20 ms/div OUT1 5.0 V/div Figure 3. Minimum Threshold Operation 20 ms/div OUT1, 2.0 V/div IN1, 5.0 V/div Figure 6. Diagnostic Operation 20 ms/div Figure 4. Low-Side Clamp http://onsemi.com 5 CS1124 APPLICATION INFORMATION Referring to Figure 2, the following will be a design example given these system requirements: RRS + 1.5 kW (u 12 kW is considered open) VRS(MAX) + 120 Vpk VRS(MIN) + 250 mVpk FVRS + 10 kHz @ VRS(MIN) + 40 Vpk-pk 1. Determine tradeoff between R1 value and power rating. (use 1/2 watt package) 120 2 2 5. Calculate C1 for low pass filtering Since the sensor guarantees 40 Vpk-pk @ 10 kHz, a low pass filter using R1 and C1 can be used to eliminate high frequency noise without affecting system performance. Gain Reduction + 0.29 V + 0.0145 + *36.7 dB 20 V Therefore, a cut-off frequency, fC, of 145 Hz could be used. C1 v 1 v 0.07 mF 2pfCR1 Set C1 = 0.047 F. 6. Calculate the minimum RRS that will be indicated as an open circuit. (DIAG = 5.0 V) PD + R1 t1 2W Rearranging equation (7) gives VHYS ) [INP1 * VRS(+TRP) RRS + INP1 KI RAdj] * R1 Set R1 = 15 k. (The clamp current will then be 120/15 k = 8.0 mA, which is less than the 12 mA limit.) 2. Determine RAdj Set RAdj as close to R1 + RRS as possible. Therefore, RAdj = 17 k. 3. Determine VRS(+TRP) using equation (7). VRS(+TRP) + 11mA 17k * 11mA(15k ) 1.5k) ) 160 mV But, VRS = 0 during this test, so it drops out. Using the following as worst case Low and High: Worst Case Low (RRS) INAdj RAdj VHYS INP1 R1 KI 23.6 A = 15 A x 1.57 16.15 k 135 mV 16 A 15.75 k 1.57 Worst Case High (RRS) 10.7 A = 7.0 A x 1.53 17.85 k 185 mV 6.0 A 14.25 k 1.53 VRS(+TRP) + 166 mV typical (easily meets 250 mV minimum) 4. Calculate worst case VRS(+TRP) Examination of equation (7) and the spec reveals the worst case trip voltage will occur when: VHYS = 180 mV INAdj = 16 A INP1 = 15 A R1 = 14.25 k (5% low) RAdj = 17.85 k (5% High) VRS(+)MAX + 16 mA(17.85 k) * 15mA(14.25 k ) 1.5 k) ) 180 mV + 229 mV RRS + 135 mV ) 23.6 mA 16 mA + 16.5 k 16.15 k * 15.75 k Therefore, RRS(MIN) + 16.5 k (meets 12 k system spec) and, RRS(MAX) + 185 mV ) 10.7 mA 6.0mA + 48.4 k 17.85 k * 14.25 k which is still less than the 250 mV minimum amplitude of the input. http://onsemi.com 6 CS1124 PACKAGE DIMENSIONS SO-8 D SUFFIX CASE 751-07 ISSUE V -X- A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. B 1 4 S 0.25 (0.010) M Y M -Y- G C -Z- H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical SO-8 45 165 Unit C/W C/W http://onsemi.com 7 CS1124 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 CS1124/D |
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